Released on = May 10, 2007, 2:06 pm

Press Release Author = Samek Mokryn

Industry = Computers

Press Release Summary = HalStor, Inc. introduces triple protocol, dual processor,
single chip, Fibre Channel (FC) to Serial ATA/Serial Attached SCSI (SATA/SAS )
gateway/controller design. The flexibility of this design enables maximizing
performance and functional flexibility for storage systems and servers utilizing FC
Storage Area Networks and using both SAS and SATA disk drives.

Press Release Body = Framingham, MA. - HalStor, Inc., a pioneer in configurable I/O
and storage solutions, introduces triple protocol, dual processor, single chip,
Fibre Channel (FC) to Serial ATA/Serial Attached SCSI (SATA/SAS ) gateway/controller
design. The flexibility of this design enables maximizing performance and functional
flexibility for storage systems and servers utilizing FC Storage Area Networks and
using both SAS and SATA disk drives.

The design addresses the need of storage system and server vendors to deploy high
performance, enterprise class systems utilizing new technologies in a timely and
cost-effective manner. It is specifically optimized for storage systems that require
custom FC/SATA/SAS controllers and protocol converters implementing functions like
encryption/decryption, access control, vendor specific commands, stream
replications, data filtering, hardware RAID, virtualization and more. As a result,
emphasis was given to providing the highest possible level of programmability and
embedded intelligence.

This design is based on our proprietary Advanced Serial Controller Architecture
(ASCA) which allows unified treatment of various serial communication protocols.
This architecture, combined with our dedicated Serial Controller Development System,
provides a significant reduction in the development effort and supports the creation
of high performance, cost-effective connectivity for internal and external storage
and storage area networks.

The HalStor FC to SATA/SAS design features:
. Maximum Performance. Direct access to RX and TX buffers assures minimum latency
and maximum bandwidth (impossible with current multi-chip solutions). In-line,
hardware supported, data and headers conversions remove unnecessary buffers and
extra stages. Multi-buffer architecture is optimized for very high performance.
. Intelligence. Dedicated dual embedded port processors (one per port) perform
complex control and error recovery functions. They cover much larger state sets than
hardware only and remove load from the host processors. Dedicated inter-processor
communication facilities allow efficient exchange of messages between the processors
unattainable in other external multi-chip solutions.
. Efficient silicon utilization. Sharing the same processor, buffers and most of
the dedicated hardware on the shared SATA/SAS port results in 90% reduction in the
silicon resources in comparison to separate cores implementation and as such provide
a dramatic decrease in the associated cost. Dedicated port processors replace large
and complex state machines, registers and counters, further reducing the size of the
silicon required.
. Flexibility. Additional functions can be implemented in a relatively
straightforward fashion. The current design can be integrated with security
protocols by allowing direct in-line implementation of encryption/decryption
hardware and integrated security related functions in microcode. Functions can be
moved between microcode and hardware, resulting in various performance/silicon size
implementations.
. Testability. The current design implementation on our Serial Controller
Development System allows direct connectivity to complementary devices (drives,
controllers) from various vendors. Changes - both hardware and microcode - can be
implemented very quickly and tested immediately. Specialized test functions and
traps can be added in hardware and microcode resulting in a dramatic decrease in
development time.
. Dual ports. The current design has one FC port and one shared SATA/SAS port.
The FC port is configured as a SCSI Target, while the SATA/SAS port is configured as
an Initiator. Other topologies are possible.
. Full FC/SAS/SATA PHY and link layer logic
. Customization for ASICs is possible

The IP of this design is available for licensing, giving the customers the unique
opportunity to expedite the design process and tailor it to their needs. HalStor is
also offering the consulting and support services, including silicon integration and
function customization, allowing customers to utilize our design and protocol
experience in their projects.

HalStor Controller Development Platform
HalStor\'s Triple FC to SATA/SAS Gateway/Controller design is implemented on
HalStor's SIMBA Development Platform featuring extended programmability and a set of
tools required to develop any fast serial interface or controller. This platform
alone provides an unprecedented tool, both extremely powerful and versatile,
allowing efficient controller development, debugging, and dramatically reducing the
cost and time of development.

For more details please visit our website at http://halstor.com


Web Site = http://halstor.com

Contact Details = Samek Mokryn
HalStor Inc.
20 Major Hale Drive
Framingham, MA 01701
email: samek@halstor.com